A high performance multi-channel preamplifier ASIC

High Performance Fuzzy ASIC

Digital's High-performance CMOS ASIC

A high-performance ASIC has been developed to serve as the interface for the 10-ns bus in the new AlphaServer 8000 series server systems from Digital. The CMOS standard-cell alternative (CSALT) technology provides a timing-driven layout methodology together with a correct-by-construction approach for managing the complex device physics issues associated with state-of-the-art CMOS processes. The...

A flexible multi-channel high-resolution Time-to-Digital Converter ASIC

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (~25ps – 800ps binning) and a dynamic range of 102.4μs has been implemented in a 0.25μm CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time...

High performance ASIC for Virtual Private Network

Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design

When there are many people who don't need to expect something more than the benefits to take, we will suggest you to have willing to reach all benefits. Be sure and surely do to take this closing the gap between asic and custom tools and techniques for high performance asic design author david chinnery jun 2002 that gives the best reasons to read. When you really need to get the reason why, thi...